1. Field of the Invention
This invention relates memory control circuits and, more particularly, to an improved address transition circuit for a memory device.
2. Prior Art
Previously, random access memories (RAMs) were purely static devices, that is, clocking techniques were not used with static RAMs. When address signals were applied to such devices, the address signals just rippled through to the memory cells to retrieve data stored therein. These devices were simple in operation, but slow and consumed large amounts of power.
Next, an address transition detection (ATD) technique was used which simulated static operation externally while clocking techniques were used inside the memory circuit to save power, chip area, and to speed up operation.
With reference to FIGS. 1 and 2, an ATD circuit 100 is shown In FIG. 1 and timing diagrams are shown in FIG. 2. An address-change input pulse is provided at node N19. This address-change input pulse is produced when a memory address bit signal changes. The memory address bit signal is sent through a delay line (not shown). The memory address bit and a delayed memory address bit from the delay line are then both inputted to an Exclusive-OR (XOR) circuit. The XOR circuit produces the address-change input pulse at node N19 which has a pulse width equal to the delay time of the delay line.
FIG. 2 is a timing chart timing showing an address bit signal changing levels and a resultant address-change input pulse at node N19. The address-change input pulse is applied to an input terminal of a resettable latch circuit 102 having a SET input terminal connected to node N19, a RESET input terminal connected to a node N6, and an OUTPUT terminal at a node N20. A latch output signal is provided at node N20 and inverted with an inverter 104 to provide a modified ATD signal called XATD at an output terminal 106. The XATD signal at terminal 106 is also directed to a delay circuit 110 to provide a delayed reset signal at the reset node N6 of the resettable latch circuit 102. The address-change input pulse at node N19 sets the XATD signal and the reset signal at node N6 resets the XATD signal. The XATD signal passes through the delay line 110 to put the signal at node N6 back to its initial condition as a logic one as shown in FIG. 2.
One embodiment of the latch circuit 102 includes three PMOS transistors M3, M4, M5 and four NMOS transistors M5, M6, M7, M8 connected as illustrated in FIG. 1.
The delay circuit 110 provides a delayed reset signal at the reset node N6 of the resettable latch circuit 102. One embodiment of the delay circuit 110 is shown in FIG. 2 and uses five inverters 112, 114, 116, 118, 120 to provide signal delays with respective MOSFET shunt loads 122, 124, 126, 128, coupled to the output terminals of the first four inverters, as illustrated in the Figure.
When the XATD output signal is high, the bit lines of the memory device are precharged to a one, as indicated in FIG. 2. When XATD goes low, the word line of the memory goes high so that some of the precharged bit lines are selectively discharged, depending upon the state of the memory bits. When XATD goes low, the charge level of the charged or discharge bit line is then detected and a corresponding signal is sent to the appropriate memory output terminal, that is, the memory content is "evaluated" as being either a one or a zero state, as indicated in FIG. 2.
Each address bit has a latch circuit for providing a corresponding XATD signal. All of the XATD signals are combined in an OR circuit to provide a global, or summarized, XATD signal.
For static operation, no restrictions are placed upon the time that address bits can occur. One address bit can arrive early and another address bit can arrive very late. This is acceptable because the specified access time to retrieve information in a memory starts from the last arriving address bit.
A chip select signal is usually associated with operation of an ATD circuit. When an ATD chip is selected, it is not known whether or not an address bit has been changed before the chip selection. To play it safe, assertion of a chip select signal causes a chip-select-change signal pulse, which is similar to an address-change pulse, to appear at the input node N19 (from a circuit not shown).
FIG. 3 is a timing chart which indicates that a problem arises when a chip select signal is asserted first and then, at a later time, an address bit subsequently changes when the reset signal at node N6 is low. If the address bit changes when N6 is low, that is, has not recovered yet, the signal at node N20 goes low. Because transistor M4 is on instead of off, the signal at output node N20 will go back up as soon as the signal at input node N19 goes low again. A narrow pulse on output node N20 causes a corresponding narrow XATD signal to appear at terminal 106. The corresponding narrow XATD signal is too short to precharge up the selectively discharged bit lines that were discharged by the #1 memory evaluation period (#1 memory evaluate in the Figure) if the #1 memory evaluation period was long enough. The result is that during the #2 memory evaluation period (#2 evaluate) the memory is incorrectly evaluated. This produces a window of non-operation so that the operation of the memory chip does not match that of a purely static operation.
One possible way to correct this situation is to ensure that signal the reset signal at node N6 is not low when a pulse arrives at input node N19. One possible way to provide this is to size the transistors in the delay line 110 so that the positive edge of the signal at node N20 ripples through the delay line quickly and the negative edge of the signal at node N20 goes through the delay line 110 with the required delay time for precharging the bit lines. This narrows the window of non-operation somewhat, but not completely.
A need exists for an improved address transition circuit which can accommodate address bit changes in an ATD circuit.